Mr. Integral
Embedded notes/Moving and Processing Data/Data Transfer and Buffering

UNIT 12 · MOVING AND PROCESSING DATA

Data Transfer and Buffering

Let hardware move the data while the CPU does the thinking.

6 lessons24 guided experiments53 min full read

A UART at a megabaud, an ADC at half a million samples a second, an audio stream that must never pause: moving that data one interrupt at a time can eat the whole CPU. A DMA controller copies it between peripherals and memory by itself, paced by the peripheral, and interrupts only when a block is done. The new questions are about buffers: how big, how they wrap, who may touch them when, and what a data cache does to the answer.

Start with lesson 1 →
∫ MR-INTEGRAL · 15 UNITS · 90 LESSONS016 lessonsPinssignals and circuits036 lessonsCPU coreand memory026 lessonsRegisters096 lessonsInterruptcontroller136 lessonsSchedulertasks and deadlines046 lessonsFlash imagebuilt by the toolchain156 lessonsSecure bootupdates and keys056 lessonsBoot ROMand reset066 lessonsDebug portprobe, trace146 lessonsPowersleep, brown-out126 lessonsDMA076 lessonsGPIOpins in and out086 lessonsClocksand timers106 lessonsUART · SPI · I²Cserial links116 lessonsADC · DACanalog
∫ MR-INTEGRAL · 15 UNITS01Pins · signals and circuits036 lessonsCPU coreand memory026 lessonsRegistersC close to the metal096 lessonsInterruptcontroller136 lessonsSchedulertasks and deadlines046 lessonsFlash imagebuilt by the toolchain156 lessonsSecure bootupdates and keys056 lessonsBoot ROMand reset066 lessonsDebug portprobe, trace146 lessonsPowersleep, brown-out126 lessonsDMA076 lessonsGPIOpins in and out086 lessonsClocksand timers106 lessonsUART · SPI · I²Cserial links116 lessonsADC · DACanalog

The unit in six ideas

  1. 1Moving data with an interrupt per byte costs rate × cycles per interrupt; at high rates that exceeds the CPU.
  2. 2The transfer direction decides which address increments: a peripheral data register stays fixed, a buffer walks.
  3. 3The transfer size must match the peripheral register and the buffer’s element type.
  4. 4For a continuous stream, a DMA channel writes a circular buffer: circular mode, address wrapping, or re-arming.
  5. 5A continuous source loses data with one buffer, for t_proc × f_s samples per block.
  6. 6A DMA buffer belongs to the CPU or the device, never both; ownership passes at start and completion.

Lessons

  1. LESSON 01 · 4 EXPERIMENTS · 9 MIN

    Moving Data Without the CPU

    What is that block, and what does it cost?

  2. LESSON 02 · 4 EXPERIMENTS · 9 MIN

    Transfer Sources, Destinations, and Requests

    Who decides when it is allowed?

  3. LESSON 03 · 4 EXPERIMENTS · 8 MIN

    Transfer Widths, Alignment, and Address Increment

    What does a DMA channel count, and what else about the buffer must match the transfer?

  4. LESSON 04 · 4 EXPERIMENTS · 9 MIN

    Circular Buffers and Producer-Consumer Flow

    What changes when the writer is a DMA channel that never stops and never asks?

  5. LESSON 05 · 4 EXPERIMENTS · 8 MIN

    Double Buffering and Continuous Streams

    How do you process a block while the next one is already arriving?

  6. LESSON 06 · 4 EXPERIMENTS · 10 MIN

    Buffer Ownership, Overruns, and Cache Coherency

    How do you keep them in agreement, and how would you even know that data was lost?