Mr. Integral
Embedded notes/Building Reliable Systems/Concurrency and Real-Time Design

UNIT 13 · BUILDING RELIABLE SYSTEMS

Concurrency and Real-Time Design

Do many things at once, and prove each one is on time.

6 lessons24 guided experiments58 min full read

Once firmware has more than one job, the hard questions are no longer about any single job but about how the jobs share the processor: who runs next, who waits, for how long, and what happens when two of them touch the same data. The answers range from a switch statement in a loop to a preemptive RTOS, and each step up buys shorter latency at the price of new ways to fail.

Start with lesson 1 →
∫ MR-INTEGRAL · 15 UNITS · 90 LESSONS016 lessonsPinssignals and circuits036 lessonsCPU coreand memory026 lessonsRegisters096 lessonsInterruptcontroller136 lessonsSchedulertasks and deadlines046 lessonsFlash imagebuilt by the toolchain156 lessonsSecure bootupdates and keys056 lessonsBoot ROMand reset066 lessonsDebug portprobe, trace146 lessonsPowersleep, brown-out126 lessonsDMA076 lessonsGPIOpins in and out086 lessonsClocksand timers106 lessonsUART · SPI · I²Cserial links116 lessonsADC · DACanalog
∫ MR-INTEGRAL · 15 UNITS01Pins · signals and circuits036 lessonsCPU coreand memory026 lessonsRegistersC close to the metal096 lessonsInterruptcontroller136 lessonsSchedulertasks and deadlines046 lessonsFlash imagebuilt by the toolchain156 lessonsSecure bootupdates and keys056 lessonsBoot ROMand reset066 lessonsDebug portprobe, trace146 lessonsPowersleep, brown-out126 lessonsDMA076 lessonsGPIOpins in and out086 lessonsClocksand timers106 lessonsUART · SPI · I²Cserial links116 lessonsADC · DACanalog

The unit in six ideas

  1. 1A state machine lists states, events, transitions and actions; one table shows the whole behaviour and every ignored event.
  2. 2A cooperative scheduler is a task table, a timer interrupt that only marks tasks due, and a loop that runs the most urgent due task to completion.
  3. 3A task is a function with its own stack and priority, so it can be preempted anywhere and resumed with its locals intact.
  4. 4Blocking on a kernel object costs no CPU; every blocking call should have a deliberate timeout.
  5. 5Any preemption point can split a read-modify-write or check-then-act sequence; protect the whole sequence or give the data one owner.
  6. 6Describe each task by worst-case execution time C, period T and deadline D; U = Σ C/T above 1 means some deadline must be missed.

Lessons

  1. LESSON 01 · 4 EXPERIMENTS · 9 MIN

    State Machines and Event-Driven Design

    How do you design firmware so that impossible situations cannot be reached?

  2. LESSON 02 · 4 EXPERIMENTS · 10 MIN

    Cooperative Scheduling and Superloops

    How far can you get with a timer, a table and a loop, and where exactly does it stop working?

  3. LESSON 03 · 4 EXPERIMENTS · 9 MIN

    Tasks, Context Switching, and Scheduling

    What if the scheduler could stop the long job in the middle, run the sampler, and resume the long job exactly where it was, without the long job being written any differently?

  4. LESSON 04 · 4 EXPERIMENTS · 10 MIN

    Queues, Semaphores, and Mutexes

    Which one is right, and what goes wrong with the others?

  5. LESSON 05 · 4 EXPERIMENTS · 10 MIN

    Race Conditions, Deadlocks, and Priority Inversion

    How can a task that uses no shared data delay one that is more important than it?

  6. LESSON 06 · 4 EXPERIMENTS · 10 MIN

    Deadlines, Execution Budgets, and Timing Analysis

    How do you show, before shipping, that every deadline will be met?