Mr. Integral
Embedded notes/Interacting with Hardware/Interrupts and Events

UNIT 09 · INTERACTING WITH HARDWARE

Interrupts and Events

React to the world the moment it changes.

6 lessons24 guided experiments43 min full read

An interrupt lets hardware stop the program and run a handler the moment something happens: a byte arrives, a timer expires, a pin changes. It is the most powerful tool in firmware and the source of its most elusive bugs: flags cleared the wrong way, a counter that loses one increment in a million, a fault input that waits behind a slow display update, a handler that runs twice for one event.

Start with lesson 1 →
∫ MR-INTEGRAL · 15 UNITS · 90 LESSONS016 lessonsPinssignals and circuits036 lessonsCPU coreand memory026 lessonsRegisters096 lessonsInterruptcontroller136 lessonsSchedulertasks and deadlines046 lessonsFlash imagebuilt by the toolchain156 lessonsSecure bootupdates and keys056 lessonsBoot ROMand reset066 lessonsDebug portprobe, trace146 lessonsPowersleep, brown-out126 lessonsDMA076 lessonsGPIOpins in and out086 lessonsClocksand timers106 lessonsUART · SPI · I²Cserial links116 lessonsADC · DACanalog
∫ MR-INTEGRAL · 15 UNITS01Pins · signals and circuits036 lessonsCPU coreand memory026 lessonsRegistersC close to the metal096 lessonsInterruptcontroller136 lessonsSchedulertasks and deadlines046 lessonsFlash imagebuilt by the toolchain156 lessonsSecure bootupdates and keys056 lessonsBoot ROMand reset066 lessonsDebug portprobe, trace146 lessonsPowersleep, brown-out126 lessonsDMA076 lessonsGPIOpins in and out086 lessonsClocksand timers106 lessonsUART · SPI · I²Cserial links116 lessonsADC · DACanalog

The unit in six ideas

  1. 1Polling costs CPU time on every check and adds up to one period of latency; interrupts cost nothing while idle and a fixed amount per event.
  2. 2An interrupt is inactive, pending, active, or active and pending; software can set and clear pending bits.
  3. 3Lower priority numbers are more urgent; more urgent interrupts preempt; equal ones never preempt, and among them the lowest IRQ number is taken first.
  4. 4A handler must clear its source; otherwise the level-held request re-enters the handler forever.
  5. 5Shared flags must be volatile; volatile does not make multi-instruction operations atomic.
  6. 6A handler blocks all interrupts of equal and lower priority for its whole duration; keep it to capture, clear and hand on.

Lessons

  1. LESSON 01 · 4 EXPERIMENTS · 7 MIN

    Polling, Interrupts, and Events

    Which one should it use, and why does an interrupt that is “enabled” sometimes never arrive?

  2. LESSON 02 · 4 EXPERIMENTS · 7 MIN

    Interrupt Requests and Handler Execution

    And when one interrupt line serves eight GPIO pins, whose job is it to find out which pin it was?

  3. LESSON 03 · 4 EXPERIMENTS · 7 MIN

    Latency, Priorities, and Nesting

    What decides how long an interrupt waits, and how do you guarantee the important one never waits long?

  4. LESSON 04 · 4 EXPERIMENTS · 7 MIN

    Acknowledging and Clearing Interrupt Flags

    How hard can writing one bit be?

  5. LESSON 05 · 4 EXPERIMENTS · 8 MIN

    Sharing Data with Interrupt Handlers

    What does it take to share even a single number with an interrupt handler?

  6. LESSON 06 · 4 EXPERIMENTS · 7 MIN

    Deferring Work and Keeping Handlers Short

    How can a handler that works correctly break everything around it?