Mr. Integral
Embedded notes/Building and Running Firmware/Debugging and Measurement

UNIT 06 · BUILDING AND RUNNING FIRMWARE

Debugging and Measurement

See what the chip is really doing, without changing it.

6 lessons24 guided experiments45 min full read

Firmware fails in ways a print statement cannot show: a variable changes and nobody knows who wrote it, the chip lands in a fault handler, an interrupt arrives a microsecond too late. This unit is about the instruments that let you see such things, and about their limits. A debugger can stop the core and read every register, but only with the comparators the core provides; a logic analyser shows every edge, but only at its sample rate; a measurement always costs time, and sometimes that cost is the bug.

Start with lesson 1 →
∫ MR-INTEGRAL · 15 UNITS · 90 LESSONS016 lessonsPinssignals and circuits036 lessonsCPU coreand memory026 lessonsRegisters096 lessonsInterruptcontroller136 lessonsSchedulertasks and deadlines046 lessonsFlash imagebuilt by the toolchain156 lessonsSecure bootupdates and keys056 lessonsBoot ROMand reset066 lessonsDebug portprobe, trace146 lessonsPowersleep, brown-out126 lessonsDMA076 lessonsGPIOpins in and out086 lessonsClocksand timers106 lessonsUART · SPI · I²Cserial links116 lessonsADC · DACanalog
∫ MR-INTEGRAL · 15 UNITS01Pins · signals and circuits036 lessonsCPU coreand memory026 lessonsRegistersC close to the metal096 lessonsInterruptcontroller136 lessonsSchedulertasks and deadlines046 lessonsFlash imagebuilt by the toolchain156 lessonsSecure bootupdates and keys056 lessonsBoot ROMand reset066 lessonsDebug portprobe, trace146 lessonsPowersleep, brown-out126 lessonsDMA076 lessonsGPIOpins in and out086 lessonsClocksand timers106 lessonsUART · SPI · I²Cserial links116 lessonsADC · DACanalog

The unit in six ideas

  1. 1GDB speaks to a debug server, which drives a probe, which talks SWD to the chip’s debug port; a MEM-AP then reads and writes the bus like any master.
  2. 2Software breakpoints replace an instruction with BKPT; they are unlimited but only work where code can be written, in practice RAM.
  3. 3A halted core’s registers are read through DCRSR/DCRDR; outer frames show only what could be reconstructed from the stack.
  4. 4On exception entry a Cortex-M stacks r0–r3, r12, LR, return address and xPSR (r0 lowest; FPU cores may push a longer frame); EXC_RETURN in LR says which stack, which mode and which frame type.
  5. 5A logic analyser stores one bit per sample; timings are uncertain by one sample period and pulses shorter than a period can disappear.
  6. 6Instrumentation runs inside what it measures: a blocking printf costs chars × 10 / baud, often milliseconds; semihosting stops the core for every call.

Lessons

  1. LESSON 01 · 4 EXPERIMENTS · 8 MIN

    Programming and Connecting to a Target

    What goes over those wires, and why does a probe sometimes refuse to connect to a board that works?

  2. LESSON 02 · 4 EXPERIMENTS · 8 MIN

    Breakpoints, Stepping, and Watchpoints

    How can a debugger stop a program at an exact instruction or on an exact memory access, and why does it sometimes say it cannot?

  3. LESSON 03 · 4 EXPERIMENTS · 7 MIN

    Inspecting Registers, Memory, and the Stack

    How do you read memory so that it means something, and how much can you trust what the debugger reconstructs?

  4. LESSON 04 · 4 EXPERIMENTS · 8 MIN

    Finding Crashes and Faults

    Where is it, and how do you read it?

  5. LESSON 05 · 4 EXPERIMENTS · 7 MIN

    Using a Logic Analyzer and Oscilloscope

    What do the instruments that watch the wires record, and how can they mislead you?

  6. LESSON 06 · 4 EXPERIMENTS · 7 MIN

    Measuring Timing Without Disturbing It

    How do you time code precisely while disturbing it as little as possible?