Transfer Sources, Destinations, and Requests

A peripheral knows when it can accept or supply data; the DMA controller does not. So a peripheral raises a data request (DREQ) when it has data to read or room to write, and a channel set to that request transfers only as fast as the peripheral asks. On the RP2040 each channel’s TREQ_SEL field chooses its pacing: 0x00–0x3a select a DREQ (for example 0x14 for UART0 transmit, 0x15 for UART0 receive, 0x24 for the ADC), 0x3b–0x3e select one of the DMA’s pacing timers, and 0x3f is a permanent request for unpaced transfers. On an STM32F4 the request is chosen by the stream and its channel number, from a table in the reference manual; in Zephyr it is the dma_slot.

↑ This step uses the figure at the top of the page.

Pick the wrong pacing and the channel runs at full speed regardless: an unpaced read from a receive FIFO mostly finds it empty (the RP2040 ADC records that as an underflow in its UNDER flag), and an unpaced write to a transmit FIFO overfills it. Unpaced (DREQ_FORCE) is for targets that are always ready: memory, or another channel’s registers.

Pacing does not make a channel instantaneous. Another master may own the bus, a higher-priority channel may be scheduled first, or the channel may be waiting to be re-armed. Meanwhile the peripheral keeps producing, and its FIFO holds the backlog. With a FIFO of $D$ entries and a new item every $T$:

The RP2040’s ADC FIFO holds 4 samples, and “if a conversion is completed and the FIFO is full, the result is dropped”, setting the OVER flag. At 500 ksps (a sample every 2 µs) that is about 8 µs of tolerance; at 250 ksps about 16 µs. The RP2040’s DMA tracks, for each channel, how many accesses it expects it can make on the peripheral “without overflow/underflow”: the handshake is a running count, not one request per transfer.

Some data must move at a steady rate without a peripheral asking: waveform samples to a PWM compare register, words to a DAC, a display line every so often. Two common sources:

• a peripheral timer’s update event can raise a DMA request (unit 8, lesson 2), and on the RP2040 each PWM slice’s wrap is a DREQ (DREQ_PWM_WRAP0 is 0x18);
• the RP2040 DMA’s own pacing timers assert a request at a fraction X/Y of the system clock, set with dma_timer_set_fraction(timer, X, Y). At 125 MHz, X/Y = 1/2500 gives 50 000 requests a second.

A channel starts when one of its trigger registers is written (or several at once through MULTI_CHAN_TRIGGER), or when another channel finishes and names it in its CHAIN_TO field. Chaining lets channels run one after another with no CPU involvement; pico-examples’ control_blocks uses one channel to reprogram another from a list in memory, sending a sequence of strings to a UART.

A finished channel stops and raises its interrupt flag. A bus error (for example, an address that no slave answers) also stops it: on the RP2040 the channel “halts when it encounters any bus error, and always raises its channel IRQ flag”, with READ_ERROR or WRITE_ERROR set; the STM32 HAL reports a transfer error through XferErrorCallback. Aborting a running channel needs care: on the RP2040, dma_channel_abort() waits until in-flight transfers have drained, and erratum RP2040-E13 means an abort can be followed by a spurious completion interrupt, which the SDK documentation tells you to expect and ignore.

pico-examples’ dma_capture runs the ADC at 500 ksps and shifts each result to 8 bits so it fits a byte buffer. The channel reads the ADC FIFO (read increment off), writes capture_buf[] (write increment on), moves 8-bit items, and is paced by DREQ_ADC:

channel_config_set_transfer_data_size(&cfg, DMA_SIZE_8);
channel_config_set_read_increment(&cfg, false);
channel_config_set_write_increment(&cfg, true);
channel_config_set_dreq(&cfg, DREQ_ADC);
dma_channel_configure(dma_chan, &cfg, capture_buf, &adc_hw->fifo, CAPTURE_DEPTH, true);

The 1000 transfers take 1000 × 2 µs = 2 ms, set by the ADC, not the DMA. With DREQ_FORCE instead, the channel would make its 1000 transfers as fast as the bus allows, microseconds rather than milliseconds, reading an empty FIFO almost every time. And if something holds the channel off for more than about 4 × 2 = 8 µs while the ADC runs, samples are dropped: check the ADC’s OVER flag after a capture, give the capturing channel high priority among the DMA channels, or raise the DMA’s bus priority (unit 3, lesson 3).