UNIT 01 · LESSON 4 OF 6

Capacitors and Decoupling

The chip runs from a regulator that is perfectly capable of supplying its current, so what is the capacitor for? And why does the layout guide insist it be close, when a wire carries current just as well from ten millimetres away as from one?

INTERACTIVEWhere does a sudden current come from?
Simplified model of a supply trace with optional local capacitor, and the resulting pin voltage during a current stepSimplified model3.3 VsupplyL = 20 nH0.2 ΩICi(t)draws a stepof 50 mA100 nFpin01002003001.52.84Pin voltage (V)Voltage at the IC pin01002003000 A50 mATime (ns)dip to 3.27 VIC current
Simplified model of a supply trace with optional local capacitor, and the resulting pin voltage during a current stepSimplified model3.3 VsupplyL = 20 nH0.2 ΩICi(t)draws a stepof 50 mA100 nFpin01002003001.52.84Pin voltage (V)Voltage at the IC pin01002003000 A50 mATime (ns)dip to 3.27 VIC current

Try this

With 100 nF at the pin and L = 20 nH: the pin voltage dips to 3.27 V (29.4 mV below 3.3 V). L and C ring at about 3.49 MHz; real boards add damping.

A simplified model: a 3.3 V supply reaches the IC through a trace with inductance L (and a little resistance); the IC suddenly draws a step of current. Without a local capacitor the whole step must come through L, and the pin voltage dips by about L·di/dt. A capacitor beside the pin supplies the first nanoseconds from its stored charge; the trace current catches up more gently. The model ignores the regulator, the plane capacitance and the rest of the board, so treat the numbers as illustrative.

What you will be able to do
  • State Q = CV and use it to relate stored charge, voltage and capacitance.
  • Sketch the exponential charging and discharging curves of an RC circuit and compute the time constant τ = RC.
  • Explain what a decoupling capacitor does during a sudden current demand and why the supply trace alone cannot do it.
  • Explain why the capacitor’s physical placement and the size of the current loop matter.
  • Recognise the limits of a decoupling capacitor and of the simplified model used here.
Before you start
  • Voltage, current, the closed loop and Ohm’s law (lesson 1).
  • Exponentials: knowing that e^{−1} ≈ 0.37 is enough.
Steps in this lesson
  1. What a capacitor stores
  2. Charging through a resistor
  3. Worked example: a reset delay
  4. The problem decoupling solves
  5. Why placement matters
  6. Choosing values, and what one capacitor cannot do
  7. Common misconceptions

The puzzle

Open almost any board and you will find a tiny capacitor, usually 100 nF, sitting right next to every chip’s power pin. The chip runs from a regulator that is perfectly capable of supplying its current, so what is the capacitor for? And why does the layout guide insist it be close, when a wire carries current just as well from ten millimetres away as from one?

STEP 1

What a capacitor stores

A capacitor is two conductive plates separated by an insulator. Push charge onto one plate and an equal charge is pulled off the other; the plates end up with a voltage between them. The amount of charge per volt is the capacitance:

Q=C⋅VQ = C \cdot V

with QQ in coulombs, CC in farads (F) and VV in volts. A farad is enormous; practical parts are microfarads (µF, 10⁻⁶), nanofarads (nF, 10⁻⁹) and picofarads (pF, 10⁻¹²). A 100 nF capacitor at 3.3 V holds Q=10−7×3.3=330Q = 10^{-7} \times 3.3 = 330 nC, and the energy stored is

E=12CV2=0.5×10−7×3.32=0.54 μJE = \tfrac{1}{2} C V^2 = 0.5 \times 10^{-7} \times 3.3^2 = 0.54\ \mu\text{J}

Not much. A capacitor is not a battery. What it offers is not a large amount of energy but fast access to a modest amount of charge: it can deliver that charge in nanoseconds, from a few millimetres away.

No charge crosses the insulator. Current appears to flow “through” a capacitor only while its voltage is changing, because charge is arriving on one plate and leaving the other:

i=Cdvdti = C \frac{dv}{dt}

Hold the voltage constant and the current is zero. That is the whole character of the part: it resists sudden changes in voltage by sourcing or sinking whatever current is needed to slow them down.

STEP 2

Charging through a resistor

INTERACTIVECharging and discharging through a resistor
RC circuit with a charge/discharge switch and the capacitor voltage and current over timechargedischarge5 VR = 1 kΩC = 100 µFv_C = 4.99 Vq = 499 µC−+i = 12.4 µA02.55v_C (V)0 s200 ms400 ms600 ms-5 mA0 A5 mAi (into C)τ: 63 %5τ: 99 %Time (τ = 100 ms)
RC circuit with a charge/discharge switch and the capacitor voltage and current over timechargedischarge5 VR = 1 kΩC = 100 µFv_C = 4.99 Vq = 499 µC−+i = 12.4 µA02.55v_C (V)0 s200 ms400 ms600 ms-5 mA0 A5 mAi (into C)τ: 63 %5τ: 99 %Time (τ = 100 ms)
Play sweeps the model time over 6 τ. Markers move in proportion to charge moved: a conceptual picture.
τ = R·C = 1 kΩ × 100 µF = 100 ms. At t = 600 ms (6 τ): v_C = 4.99 V, i = 12.4 µA, q = C·v_C = 499 µC. Peak current Vs / R = 5 mA.

Move the switch to “charge” and the source pushes charge onto the top plate while pulling the same amount off the bottom plate; no charge crosses the gap. The current starts at Vs / R and shrinks as the capacitor voltage rises toward Vs, following an exponential with time constant τ = R·C. After one τ the voltage has covered 63 % of the way; after 5τ, 99 %. Discharge follows the same curve downward. Markers move in proportion to the charge that has flowed; they are conceptual.

Connect a discharged capacitor to a source through a resistor. At the first instant the capacitor holds 0 V, so the entire source voltage is across the resistor and the current is Vs/RV_s / R: its largest value. As charge arrives the capacitor voltage rises, the voltage left for the resistor falls, and the current falls with it. The result is an exponential approach:

vC(t)=Vs(1−e−t/τ)v_C(t) = V_s \left(1 - e^{-t/\tau}\right) i(t)=VsR e−t/τi(t) = \frac{V_s}{R}\, e^{-t/\tau} τ=R C\tau = R\,C

τ\tau, the time constant, has units of seconds (ohms times farads). After one τ\tau the capacitor has covered 1−e−1≈63 %1 - e^{-1} \approx 63\,\% of the way; after 5τ5\tau it is within 1 %. Discharge is the same curve upside down: vC=Vs e−t/τv_C = V_s\, e^{-t/\tau}, with the current now flowing the other way as the capacitor pushes its charge back out through the resistor.

Watch the markers in the figure: they move quickly at first and slow as the capacitor fills, and they never cross the gap between the plates. What happens is that charge piles up on the top plate while the same amount is drawn off the bottom plate through the return wire.

STEP 3

Worked example: a reset delay

A reset pin is held low by a 100 nF capacitor charged through a 47 kΩ pull-up. The chip leaves reset when the pin passes about 63 % of the supply. How long after power-up does that happen?

τ=R C=47 000×10−7=4.7 ms\tau = R\,C = 47\,000 \times 10^{-7} = 4.7\ \text{ms}

The 63 % point is reached at t=τ=4.7t = \tau = 4.7 ms. To reach 90 %: 1−e−t/τ=0.91 - e^{-t/\tau} = 0.9 gives t=τln⁡10=2.3 τ≈10.8t = \tau \ln 10 = 2.3\,\tau \approx 10.8 ms. Set the figure to 47 kΩ and 100 nF and read the same curve.

STEP 4

The problem decoupling solves

A digital chip draws current in bursts. Every clock edge, thousands of transistors switch, each pulling a little charge from the supply pins, and the demand can jump from a few milliamps to tens of milliamps in a nanosecond. Inside the chip nothing can wait for that current; the logic simply runs on whatever voltage is at the pins.

The supply reaches those pins through a trace, and every trace has inductance. Inductance is the electrical property that resists a change in current, and a length of trace a few centimetres long has on the order of 10–30 nH. Its effect is a voltage drop proportional to how fast the current changes:

v=Ldidtv = L \frac{di}{dt}

A linear current ramp of 50 mA in 2 ns through 20 nH drops 20×10−9×0.05/(2×10−9)=0.520 \times 10^{-9} \times 0.05 / (2 \times 10^{-9}) = 0.5 V. The regulator is still holding 3.3 V at its own output, but the chip sees 2.8 V for a moment, and if that moment lands on a clock edge the chip can misbehave, corrupt a memory access or reset.

The interactive uses a smoothly rounded current step instead of a linear ramp. Its peak slope is 1.5 times its average slope, so its peak inductive dip is correspondingly larger.

↑ This step uses the figure at the top of the page.

The decoupling capacitor (also called a bypass capacitor) sits right at the chip’s power pins and acts as a local reservoir of charge, which is exactly how the Analog Devices tutorial describes it. When the chip demands current, the first nanoseconds come from the capacitor, whose stored charge is millimetres away and reachable through almost no inductance. The current through the long supply trace then ramps up gently while the capacitor refills. In the figure, switch the capacitor off and on and compare the dip.

STEP 5

Why placement matters

DIAGRAMSame capacitor, two placements
Decoupling capacitor placed far from and close to an IC, showing the current loop area01 FAR FROM THE PINSSame IC · same capacitor · different placementSUPPLYRETURNC1VDDICGNDlong pathLarger loop · higher loop inductance02 CLOSE TO THE PINSSame IC · same capacitor · different placementSUPPLYRETURNC1VDDICGNDshort pathSmaller loop · lower loop inductance
Decoupling capacitor placed far from and close to an IC, showing the current loop area01 FAR FROM THE PINSSame IC · same capacitor · different placementSUPPLYRETURNC1VDDICGNDlong pathLarger loop · higher loop inductance02 CLOSE TO THE PINSSame IC · same capacitor · different placementSUPPLYRETURNC1VDDICGNDshort pathSmaller loop · lower loop inductance
Shading marks the transient-current loop; arrows show its direction. The dashed path inside the IC is conceptual. Short supply and return connections reduce external loop inductance.

Top view of a board. The IC’s sudden current demand is supplied by the nearest charge reservoir, and that current has to travel around a loop: out of the capacitor, along the supply trace, through the IC, and back along the ground trace. The loop geometry, including area and conductor spacing, affects its inductance, and inductance resists a fast change of current. Short supply and return connections reduce the loop inductance; package and connection inductance still remain.

The transient current does not travel from the capacitor to the pin; it travels around a loop: out of the capacitor, along the supply trace to the pin, through the chip, out of the ground pin, back along the ground trace to the capacitor. The inductance of that loop grows with the area it encloses. A capacitor at the far end of the board encloses a big loop and behaves, from the chip’s point of view, like a capacitor with an inductor in series: the very thing it was meant to bypass. A capacitor at the pins, with short fat connections to both the supply pin and the ground pin, encloses almost nothing.

This is why every layout guide says the same thing. MT-101 asks for the capacitor to be as physically close to the power pins as possible, with connections to both the power pin and ground kept as short as possible. The RP2040 hardware design guide recommends a 100 nF capacitor per power pin and stresses placing decoupling close to the power pins; the RP2040 datasheet repeats “close to” for each individual supply pin. The wording is about the loop, not the wire length as such: a short wire that forms a large loop with its return is still a large inductance.

STEP 6

Choosing values, and what one capacitor cannot do

The 100 nF ceramic capacitor is the workhorse because it is cheap, small, has low series inductance, and covers the frequencies at which typical logic switches. Chips with heavier or slower demands add a larger capacitor (1–10 µF) nearby for the microsecond-scale dips, with the 100 nF still handling the nanosecond ones. The regulator’s own output capacitor handles the slowest changes.

Some limits to keep in mind:

  • A capacitor is a small reservoir, not a source. It supplies the first nanoseconds; the regulator must still deliver the average current, and a steady overload will drain the capacitor in microseconds.
  • Every capacitor has series inductance (ESL) from its body and connections. Above its self-resonant frequency, f=1/(2πLESLC)f = 1 / (2\pi\sqrt{L_{ESL} C}), it behaves as an inductor, so choose parts using their impedance curves and mounted inductance; capacitance alone does not determine high-frequency performance.
  • Many high-permittivity ceramic capacitors lose capacitance under DC voltage. Murata’s data shows a 6.3 V-rated 100 µF X5R part losing about 10 % of its capacitance at 1.8 V and a Y5V part about 40 %. The nominal value is not what you get on the rail.
  • No single value fixes every power-integrity problem. A dip that survives correct decoupling usually means a loop that is too large, a ground path that is too thin, or a load the regulator cannot follow.

MYTHS AND FACTS

Common misconceptions

A decoupling capacitor can power the chip indefinitely

It stores finite energy. The useful support time depends on capacitance, load current and allowed voltage droop; for a roughly constant current, Δt≈CΔV/I\Delta t \approx C\Delta V/I.

Current flows through the capacitor

Charge arrives on one plate and leaves the other; the current in the wires is real, but nothing crosses the insulator.

The regulator is fast, so the capacitor is redundant

The regulator is centimetres away through inductance it cannot control. Speed at the regulator’s output is not speed at the pin.

Wire length is what matters

Loop area is what matters. A short wire with a distant return is still a large loop.

Bigger capacitors decouple better

Above their self-resonant frequency they are inductors. Small, close and low-inductance beats large and far.

Check yourself

Answer in your head, then open the card.

A 10 kΩ resistor charges a 1 µF capacitor from 5 V. What is τ, and what is the capacitor voltage after 10 ms?

τ=104×10−6=10\tau = 10^4 \times 10^{-6} = 10 ms. After one τ, vC=5(1−e−1)=3.16v_C = 5 (1 - e^{-1}) = 3.16 V.

At the instant the switch closes on a discharged capacitor, what is the current, and why is it the maximum?

I=Vs/RI = V_s / R. The capacitor is at 0 V, so the entire source voltage is across the resistor. As the capacitor charges, less voltage remains for the resistor and the current falls.

A chip draws a 40 mA step in 4 ns through a supply trace with 10 nH of inductance and no local capacitor. Estimate the dip at the pin.

v=L di/dt=10×10−9×0.04/(4×10−9)=0.1v = L\,di/dt = 10 \times 10^{-9} \times 0.04 / (4 \times 10^{-9}) = 0.1 V. A 100 mV dip on a 3.3 V rail; faster or larger steps make it worse.

A capacitor sits 30 mm from the chip but is connected by a very short wire to the ground plane. Is the loop small?

Not necessarily. The loop runs from the capacitor along the supply trace to the pin and back through the plane. The 30 mm of supply trace still encloses area with the plane beneath it. Moving the capacitor next to the pin shrinks the loop; a short ground wire alone does not.

Sources (5)
  1. Tony R. Kuphaldt, Lessons in Electric Circuits, Vol. I (DC), ch. 13 “Capacitors” — stored charge, Q = CV, and the capacitor’s opposition to a change in voltage
  2. Tony R. Kuphaldt, Lessons in Electric Circuits, Vol. I (DC), ch. 16 “RC and L/R Time Constants” — the exponential charge and discharge curves and the time constant τ = RC
  3. Analog Devices, Tutorial MT-101 “Decoupling Techniques” (Rev. 0, 03/2009) — the capacitor as a local reservoir of charge; placement as close as possible to the power pins; ESL and self-resonance
  4. Raspberry Pi Ltd, “Hardware design with RP2040” (Release 2), §2.1.2 “Decoupling capacitors”, p. 7 — example of a manufacturer’s guidance: a 100 nF capacitor per power pin, placed close to the power pins; the RP2040 datasheet §2.9 says the same per pin
  5. Murata, “The voltage characteristics of electrostatic capacitance” (technical article, 28 November 2012) — DC-bias effect: a 6.3 V-rated 100 µF X5R MLCC loses about 10 % of its capacitance at 1.8 V, a Y5V part about 40 %