Mr. Integral
Embedded notes/Moving and Processing Data/Analog Signals and Conversion

UNIT 11 · LESSON 3 OF 6

References, Input Impedance, and Acquisition Time

What are the ADC’s reference and input really doing?

INTERACTIVEThe sample capacitor needs time to charge
Charging of the ADC sampling capacitor during the acquisition timesampling endsfinalτ = (10.0 kΩ + 1 kΩ) × 10 pF = 110 ns; sampling 15 cycles at 21 MHz = 714 nsleft to settle: 6.2 LSB of a full-scale step; ½ LSB at 12 bits needs 991 ns (9.0 τ)Too short: the reading is pulled toward the previous channel’s voltage. Lengthen thesampling time or buffer the source.
Charging of the ADC sampling capacitor during the acquisition timesampling endsfinalτ = (10.0 kΩ + 1 kΩ) × 10 pF = 110 ns; sampling 15cycles at 21 MHz = 714 nsleft to settle: 6.2 LSB of a full-scale step; ½ LSBat 12 bits needs 991 ns (9.0 τ)Too short: the reading is pulled toward the previouschannel’s voltage. Lengthen the sampling time orbuffer the source.

Try this

Sampling time
ADC clock
Settling error 6.20 LSB; too short.

A SAR ADC connects a small sampling capacitor to the input for the sampling (acquisition) time, then converts the charge it holds. The capacitor charges through the source resistance and the ADC’s internal switch, so it needs several time constants to come within half an LSB. The capacitance and switch resistance here are illustrative; the datasheet gives the real ones. STM32F4 sampling times are chosen in ADC clock cycles; at 12-bit resolution a conversion then takes 12 more.

What you will be able to do
  • Explain why every reading is relative to the reference and how reference errors appear.
  • Use a ratiometric arrangement to cancel supply variation for resistive sensors.
  • Describe how a SAR ADC samples onto a capacitor and why the source resistance matters.
  • Compute the acquisition time needed to settle within half an LSB and choose a sampling-time setting.
  • Choose between a longer sampling time, a buffer amplifier and a reservoir capacitor for a high-impedance source.
Before you start
  • RC charging (unit 1, lesson 4) and voltage dividers (unit 1, lesson 3).
  • Resolution and accuracy (lesson 2).
Steps in this lesson
  1. The reference is the ruler
  2. Ratiometric measurement
  3. How the input is sampled
  4. High-impedance sources
  5. Worked example: sampling the 10 kΩ divider
  6. Common misconceptions

The puzzle

A thermistor divider reads correctly when the board runs from USB and 2 °C off on battery. A second sensor, a 100 kΩ divider, reads correctly alone but is pulled toward the neighbouring channel’s voltage when both are sampled in turn. Neither is noise. What are the ADC’s reference and input really doing?

STEP 1

The reference is the ruler

Every code is a fraction of the reference: Vin = code × Vref / 2^N. A reference 1 % high makes every reading 1 % low. Microcontroller ADCs often use the analog supply (for the RP2040 examples, “ADC_VREF == 3.3 V”) or an internal reference, sometimes selectable per channel, as Zephyr’s ADC API shows. A supply-derived reference carries the supply’s tolerance, ripple and load-dependent drops into every measurement.

STEP 2

Ratiometric measurement

A resistive sensor in a divider produces a voltage proportional to the voltage feeding it. If the divider is fed from the same voltage the ADC uses as its reference, both scale together and cancel:

code=2N Vsupply R2/(R1+R2)Vref=2N R2R1+R2when Vsupply=Vref\text{code} = 2^{N}\,\frac{V_{\text{supply}}\,R_2/(R_1+R_2)}{V_{\text{ref}}} = 2^{N}\,\frac{R_2}{R_1+R_2} \quad \text{when } V_{\text{supply}} = V_{\text{ref}}

Potentiometers, thermistors and strain gauges are best measured this way. An absolute voltage, such as a battery or a sensor with its own output stage, needs an accurate reference instead.

INTERACTIVERatiometric measurement cancels the reference
ADC reading of a resistive divider with a ratiometric and a fixed supplycode 2048 = 50.00 % of full scaletrue resistor ratio: 50.00 %divider fed from 3.2 V, ADC reference 3.2 V: input 1.6 VRatiometric: the reading stays at the true ratio (within one LSB) whatever the supply.
ADC reading of a resistive divider with a ratiometric and a fixed supplycode 2048 = 50.00 % of full scaletrue resistor ratio: 50.00 %divider fed from 3.2 V, ADC reference 3.2 V: input1.6 VRatiometric: the reading stays at the true ratio(within one LSB) whatever the supply.
Code 2048 (nominal 2048).

A resistive sensor in a divider gives a voltage proportional to its supply. If the divider and the ADC reference are the same voltage, the code depends only on the resistor ratio: supply changes cancel. Feed the divider from a different supply, or measure an absolute voltage, and every change in the reference becomes a reading error.

STEP 3

How the input is sampled

A successive-approximation (SAR) ADC, like those in most microcontrollers, first connects the input to a small sampling capacitor through an internal switch for the sampling (acquisition) time, then disconnects it and converts the stored charge. During acquisition the capacitor charges through the source resistance plus the switch resistance, an RC circuit. If it starts from a different voltage, for example the previous channel’s, the error decays as

ε(t)=ΔV e−t/τ,\varepsilon(t) = \Delta V\, e^{-t/\tau}, τ=(Rsource+Rswitch) Csample\tau = (R_{\text{source}} + R_{\text{switch}})\,C_{\text{sample}}

and, for a full-scale step (ΔV = Vref, the worst case), falls below half an LSB of an N-bit converter after

tacq≥τln⁡2N+1≈9.0 τ(N=12)t_{\text{acq}} \ge \tau \ln 2^{N+1} \approx 9.0\,\tau \quad (N = 12)

↑ This step uses the figure at the top of the page.

STEP 4

High-impedance sources

When the source is too resistive for the available sampling time:

  • lengthen the sampling time, if the converter allows it (STM32F4 channels choose from 3 to 480 ADC clock cycles) and the sample rate can afford it;
  • buffer the source with an op-amp follower, which presents a low output impedance to the ADC;
  • add a reservoir capacitor at the ADC pin, much larger than the sampling capacitor, which supplies the charge; the divider then has to recharge it between samples, so the source must be slow or the sample rate low.

Internal channels (temperature sensors, internal references) often need a minimum sampling time from the datasheet; ST’s HAL gives the rough order as 4 µs.

STEP 5

Worked example: sampling the 10 kΩ divider

Take a source resistance of 10 kΩ, an illustrative 1 kΩ switch and 10 pF sampling capacitor: τ = 11 kΩ × 10 pF = 110 ns, and settling within ½ LSB at 12 bits needs 9.0 × 110 ns ≈ 0.99 µs. With a 21 MHz ADC clock, 15 cycles give 714 ns: only 6.5 τ, leaving about 6 LSB of a full-scale step unsettled. 28 cycles give 1.33 µs, enough. The conversion then takes 28 + 12 = 40 cycles, 1.9 µs, so the channel can be sampled at up to about 525 kS/s.

MYTHS AND FACTS

Common misconceptions

The reference is exactly 3.3 V

It is whatever the supply or reference actually delivers, with its tolerance and noise.

ADC inputs draw no current

They draw charging current pulses at every sample; averaged, that looks like a load resistance.

A higher resistance divider saves power at no cost

It lengthens the acquisition time and raises noise pick-up.

A capacitor at the input fixes everything

It provides the sampling charge but slows the input’s response to real changes.

Check yourself

Answer in your head, then open the card.

A potentiometer is fed from 3.3 V and read by an ADC whose reference is the same 3.3 V rail. The rail drops to 3.1 V. How much does the reading change?

Not at all (to within an LSB): the input and the reference drop together, so the code depends only on the wiper position.

With τ = 50 ns, how long must the acquisition be for ½ LSB at 10 bits?

ln(2^11) ≈ 7.6: t ≥ 7.6 × 50 ns ≈ 0.38 µs.

Why can a high-impedance channel read the voltage of the channel sampled just before it?

The sampling capacitor still holds the previous channel’s voltage; with too little acquisition time it cannot charge to the new input, so the reading lies between the two.

An STM32F4 ADC runs at 36 MHz and a channel uses 56 sampling cycles at 12 bits. What is its conversion time?

(56 + 12) / 36 MHz ≈ 1.89 µs.

Sources (3)
  1. STMicroelectronics, stm32f4xx-hal-driver, Inc/stm32f4xx_hal_adc.h — ADC_SAMPLETIME_3CYCLES … 15, 28, 56, 84, 112, 144, 480CYCLES; SamplingTime “Unit: ADC clock cycles”; “Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits …)”; internal channels need their datasheet minimum sampling time (“values rough order: 4us min”)
  2. Zephyr Project, include/zephyr/drivers/adc.h — struct adc_channel_cfg: reference (ADC_REF_VDD_1, VDD/2 … ADC_REF_INTERNAL, ADC_REF_EXTERNAL0/1) and acquisition_time, set with ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 20) or ADC_ACQ_TIME_DEFAULT: the reference and the acquisition time are per-channel choices
  3. Raspberry Pi Ltd, pico-examples, adc/onboard_temperature/onboard_temperature.c — “12-bit conversion, assume max value == ADC_VREF == 3.3 V”; conversionFactor = 3.3f / (1 << 12); T = 27 − (V − 0.706)/0.001721