Analog Outputs and PWM Filtering

The puzzle

A motor-speed reference, an LED dimmer and an audio beep: all need a voltage that firmware can set, and the RP2040 has no DAC at all. The usual answer is a PWM pin and a resistor and capacitor. The first attempt at 12-bit resolution gives a voltage that visibly wobbles; the second is smooth but takes a sluggish tenth of a second to change. Where is the balance?

STEP 1

PWM as a DAC

A PWM output switching between 0 and V_supply with duty cycle D has an average of D × V_supply. An RC low-pass passes the average and attenuates the switching, but not completely: some ripple at the PWM frequency remains. For a first-order RC filter with time constant τ and PWM period T, the exact peak-to-peak ripple is

V_{\text{ripple}} = V_{\text{supply}}\,\frac{(1 - e^{-DT/\tau})(1 - e^{-(1-D)T/\tau})}{1 - e^{-T/\tau}} \approx V_{\text{supply}}\,\frac{D(1-D)\,T}{\tau} \quad (T \ll \tau)

largest at 50 % duty. Unit 8 showed the same formula from the PWM side.

↑ This step uses the figure at the top of the page.

STEP 2

The three-way trade

Resolution needs many counter steps per period: an N-bit PWM needs 2^N cycles, so at 125 MHz a 12-bit PWM runs at only 30.5 kHz.
Low ripple needs τ much longer than the period, ideally below half a step (V_supply / 2^(N+1)).
Fast response needs a short τ: the output takes about τ ln 2^(N+1) to settle within half a step after the duty cycle changes.

Higher resolution lowers the PWM frequency, which demands a larger τ, which slows the response. A second RC stage (or an active filter) attenuates ripple far more for the same response time; so does choosing the lowest resolution the task really needs.

STEP 3

A real DAC

A digital-to-analog converter produces the voltage directly, with no ripple to filter. For waveforms it must be updated at a steady rate: ST’s HAL lets a timer’s TRGO trigger each conversion, and DMA feeds it values. Its output may have a significant impedance: the STM32F4’s DAC has an optional output buffer to drive loads directly. Where there is no internal DAC, an external one on SPI or I²C (unit 10) gives precision beyond what PWM can reach, at the cost of a part and a bus transfer per update.

STEP 4

The staircase and its images

A DAC holds each value until the next update, a zero-order hold. The staircase differs from the intended smooth waveform in two ways: the wanted frequency f is slightly attenuated, and copies (images) appear around multiples of the update rate f_s, the first at f_s − f:

\text{droop}(f) = \frac{\sin(\pi f/f_s)}{\pi f / f_s}

INTERACTIVEA DAC output is a staircase

Updates per signal period

Droop -0.06 dB; image at 15 kHz.

A DAC holds each value until the next update, so a sine comes out as a staircase. The steps attenuate the wanted frequency slightly (by sin(πf/f_s)/(πf/f_s), the zero-order-hold droop) and add images around multiples of the update rate, the first at f_s − f. A reconstruction low-pass filter after the DAC removes the images; the more samples per period, the easier its job.

A reconstruction filter, an analog low-pass after the DAC, removes the images; the more updates per period of the highest wanted frequency, the further the images are from the signal and the simpler the filter. Droop can be corrected digitally before the DAC; images around the actual update rate can only be removed in analog, although interpolating to a higher update rate first moves them further away.

STEP 5

Worked example: an 8-bit PWM reference

With wrap = 255 at 125 MHz, the PWM runs at 125 MHz / 256 ≈ 488 kHz (T = 2.05 µs) in steps of 3.3 V / 256 = 12.9 mV. With τ = 1 ms at 50 % duty:

V_{\text{ripple}} \approx 3.3 \times \frac{0.25 \times 2.05\ \mu\text{s}}{1\ \text{ms}} \approx 1.7\ \text{mV}

about 0.13 of a step, well below half. Settling within half a step takes 1 ms × ln 512 ≈ 6.2 ms. A 12-bit PWM with only τ = 100 µs, in contrast, has a ripple of 270 mV, more than 300 of its 0.8 mV steps: the extra resolution is invisible.

MYTHS AND FACTS

Common misconceptions

A 12-bit PWM gives a 12-bit DAC

Only if the filter reduces the ripple below half a step, which makes it slow.

A bigger capacitor is the fix

It trades ripple for response time; a second filter stage or a higher PWM frequency may be better.

A DAC output is a smooth waveform

It is a staircase with images that need a reconstruction filter.

Any pin can drive the DAC’s load

DAC outputs can have high impedance; enable the buffer or add an amplifier.

Check yourself

Answer in your head, then open the card.

An RP2040 PWM runs from a 125 MHz clock with wrap = 1023. What are its frequency and step size at 3.3 V?

125 MHz / 1024 ≈ 122 kHz; 3.3 V / 1024 ≈ 3.2 mV per step.

Using the approximation, what τ keeps the ripple of that PWM below half a step at 50 % duty?

3.3 × 0.25 × 8.19 µs / τ < 1.6 mV gives τ > about 4.2 ms.

A DAC updates at 8 kHz to play a 1 kHz tone. Where is the first image, and how much droop is there?

At 8 − 1 = 7 kHz; droop sin(π/8)/(π/8) ≈ 0.974, about −0.22 dB.

Why can a digital filter before the DAC correct droop but not images?

Droop is a known frequency response of the signal the DAC is asked to produce, which can be pre-emphasised; images around the update rate are created by the hold itself in the analog output, after any digital processing (interpolating to a higher rate only moves them).

Sources (3)

Raspberry Pi Ltd, pico-sdk 1.5.1, hardware_pwm/pwm.h — “The default behaviour of a PWM slice is to count upward until the wrap value … is reached, and then immediately wrap to 0”; the wrap is “the highest value the counter will reach before returning to 0. Also known as TOP”, so (outside phase-correct mode) a period is wrap + 1 counter cycles
STMicroelectronics, stm32f4xx-hal-driver, Src/stm32f4xx_hal_dac.c — conversion “can be triggered by … Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8” or software; “Each DAC channel integrates an output buffer that can be used to reduce the output impedance, and to drive external loads directly” (DAC_OUTPUTBUFFER_ENABLE); refer to the datasheet for the output impedance
Arm, CMSIS-DSP, Source/FilteringFunctions/arm_fir_f32.c — an FIR filter on the sample stream, “y[n] = b[0] * x[n] + b[1] * x[n-1] + …”, is the tool for shaping the samples’ frequency response before the DAC