Mr. Integral
Embedded notes/Moving and Processing Data/Serial Communication

UNIT 10 · LESSON 4 OF 6

I²C and Two-Wire Addressed Communication

Two wires, dozens of devices, no chip selects: how does I²C work, and how does it fail?

INTERACTIVEAn I²C register read, byte by byte
The sequence of an I²C transaction with start, address, acknowledge, data and stopS0x90addr 0x48+WA0x00registerASr0x91addr 0x48+RA··data 0A··data 1NAPblue: sent by the controller, teal: by the device5 bytes, about 480 µs at 100 kHz; the address is sent as 0x90 and 0x91
The sequence of an I²C transaction with start, address, acknowledge, data and stopS0x90addr 0x48+WA0x00registerASr0x91addr 0x48+RA··data 0A··data 1NAPblue: sent by the controller, teal: by the device5 bytes, about 480 µs at 100 kHz; the address issent as 0x90 and 0x91

Try this

Operation
7-bit address
Bus speed
5 bytes, ≈ 480 µs.

Every I²C transfer starts with a start condition and the device’s 7-bit address followed by a read/write bit, so address 0x48 appears on the wire as 0x90 (write) or 0x91 (read). The receiver of each byte answers with an acknowledge (A) or not-acknowledge (NA). A register read writes the register number, then turns the bus round with a repeated start (Sr) and reads; the controller NAs the last byte before the stop (P).

What you will be able to do
  • Explain why I²C lines are open-drain with pull-ups, and choose a pull-up resistor from the rise-time limit.
  • Decode an I²C transaction: start, address and read/write bit, acknowledge, data, repeated start and stop.
  • Convert between a device’s 7-bit address and the byte on the wire, and avoid reserved addresses.
  • Interpret a missing acknowledgement and the errors an SDK returns.
  • Recover a bus held low by a device interrupted mid-transfer.
Before you start
  • Pull-up resistors (unit 1, lesson 3) and open-drain outputs (unit 7, lesson 2).
  • Synchronous serial links (lessons 1 and 3).
Steps in this lesson
  1. Two open-drain wires
  2. Pull-ups and rise time
  3. Start, address, acknowledge
  4. Register reads and the repeated start
  5. Reserved addresses and bus scans
  6. A bus stuck low
  7. Worked example: the pull-up for a 400 kHz bus
  8. Common misconceptions

The puzzle

A temperature sensor at address 0x48 works on the bench and returns errors in the product. A colleague says its address is 0x90. After a reset in the middle of a read, the bus stays low and nothing responds until the power is cycled. Two wires, dozens of devices, no chip selects: how does I²C work, and how does it fail?

STEP 1

Two open-drain wires

I²C uses a clock (SCL) and a data line (SDA), shared by every device. In Standard, Fast and Fast-mode Plus (the speeds most microcontrollers support), no device drives a line high: outputs are open-drain, pulling low or letting go (unit 7, lesson 2), and a pull-up resistor on each line brings it high when nobody pulls. This makes the bus safe for many devices (two devices driving at once cannot short each other) and lets any device hold a line low: the receiver acknowledges by pulling SDA low, and a slow device may hold SCL low to pause the controller, which is clock stretching (not every controller supports it; Linux marks such adapters I2C_AQ_NO_CLK_STRETCH).

STEP 2

Pull-ups and rise time

A line falls fast (a transistor pulls it down) but rises only as fast as the pull-up can charge the bus capacitance, the sum of the wiring and every connected pin. The rise from 30 % to 70 % of the supply takes

tr=RCln⁡0.70.3≈0.847 RCt_r = RC \ln\frac{0.7}{0.3} \approx 0.847\,RC

and the I²C specification limits it: 1000 ns at up to 100 kHz, 300 ns at up to 400 kHz and 120 ns in Fast-mode Plus (the defaults Linux derives from the specification).

INTERACTIVEPull-up resistors and rise time
The rising edge of an I²C line charged through a pull-up resistor30 %70 %limitrise time 0.847 RC = 796 ns; limit at 400 kHz: 300 ns — too slowa device pulling the line low sinks about 3.3 V / R = 0.70 mA; check that every deviceon the bus can sink that
The rising edge of an I²C line charged through a pull-up resistor30 %70 %limitrise time 0.847 RC = 796 ns; limit at 400 kHz: 300ns — too slowa device pulling the line low sinks about 3.3 V / R= 0.70 mA; check that every device on the bus cansink that
Speed
Rise time 796 ns vs limit 300 ns: too slow.

In Standard, Fast and Fast-mode Plus I²C, devices only pull the lines low; a pull-up resistor brings them high again, charging the bus capacitance (wiring and every device’s pins). The rising edge is an RC curve: a larger resistor or a longer bus rises more slowly, and the I²C specification limits the 30 %→70 % rise time for each speed. A smaller resistor rises faster but every device must sink its current when pulling low.

A smaller resistor rises faster but draws more current through every device that pulls the line low, and each device can sink only so much (its datasheet gives the limit). The weak internal pull-ups some examples enable are fine for a short bench setup and too weak for most real buses.

STEP 3

Start, address, acknowledge

While SCL is high, SDA must not change, except to mark the ends of a transaction: SDA falling while SCL is high is a start (S), SDA rising while SCL is high is a stop (P). After the start, the controller sends the device’s 7-bit address followed by a read/write bit (1 = read, 0 = write), most significant bit first. So a device at address 0x48 appears on the wire as 0x90 for a write and 0x91 for a read; datasheets that quote “0x90” are giving the shifted byte.

After every byte, the receiver drives the ninth clock’s data bit: low is an acknowledge (A), high is a not-acknowledge (NA). A missing acknowledgement after the address means no device answered at that address; the pico-sdk’s blocking functions return PICO_ERROR_GENERIC.

↑ This step uses the figure at the top of the page.

STEP 4

Register reads and the repeated start

Most devices are read like memory: write the register number, then read. Between the two, the controller sends a repeated start (Sr) instead of stop-then-start, keeping control of the bus so that no other controller can intervene; some devices also require it to keep the register pointer, although many keep it across a stop. The pico-sdk does this when the write is called with nostop = true. When reading, the controller acknowledges every byte except the last, which it NAs before the stop, telling the device to release SDA.

STEP 5

Reserved addresses and bus scans

Addresses of the form 000 0xxx and 111 1xxx are reserved for special purposes (general call, 10-bit addressing and others), leaving 112 usable 7-bit addresses. A bus scan tries every non-reserved address and lists those that acknowledge, the first thing to run when a device does not answer. Two devices with the same fixed address cannot share a bus; many devices have address pins to choose among a few addresses.

STEP 6

A bus stuck low

If the controller resets in the middle of a read, the device may still be driving SDA low, waiting for clock pulses to finish its byte. The controller then sees a busy bus and cannot even send a start. The standard recovery is to clock SCL manually up to nine times until the device releases SDA, then generate a stop; Linux’s generic recovery does exactly that. If SCL itself is held low, a device is stretching or stuck, and only resetting it or cycling its power helps.

STEP 7

Worked example: the pull-up for a 400 kHz bus

A bus with 200 pF must rise within 300 ns at 400 kHz:

R≤tr0.847 C=300 ns0.847×200 pF≈1.77 kΩR \le \frac{t_r}{0.847\,C} = \frac{300\ \text{ns}}{0.847 \times 200\ \text{pF}} \approx 1.77\ \text{k}\Omega

The common 4.7 kΩ gives 0.847 × 4.7 kΩ × 200 pF ≈ 796 ns: fine at 100 kHz (limit 1000 ns) but far too slow at 400 kHz. With a 1.5 kΩ pull-up at 3.3 V, a device pulling low sinks about 2.2 mA; check that every device on the bus can sink that.

MYTHS AND FACTS

Common misconceptions

The address is 0x90

That is 0x48 shifted left with the write bit; the pico-sdk and Linux take the 7-bit value.

Stronger pull-ups are always better

They speed the rising edge but increase the current every device must sink.

A NACK means the device is broken

It means nobody answered at that address: wrong address, missing pull-ups, a device held in reset, or wiring.

Power-cycling the controller frees a stuck bus

The device holding SDA keeps doing so until it receives clocks or is reset itself.

Check yourself

Answer in your head, then open the card.

What byte does the controller send to read from a device at 7-bit address 0x68?

(0x68 << 1) | 1 = 0xD1.

Why does a register read use a repeated start rather than a stop between writing the register number and reading?

The controller keeps the bus, so no other controller can start a transfer in between and change the device’s register pointer; some devices also reset the pointer on a stop.

A 100 kHz bus has 350 pF of capacitance. What is the largest pull-up that meets the 1000 ns rise-time limit?

1000 ns / (0.847 × 350 pF) ≈ 3.4 kΩ.

After a watchdog reset during an I²C read, SDA stays low. What should the firmware do at start-up?

Before initialising the I²C controller, drive SCL as a GPIO: pulse it up to nine times until SDA goes high, then generate a stop condition, and only then enable the controller.

Sources (4)
  1. Linux kernel, Documentation/i2c/i2c-protocol.rst — symbols S, P, Rd/Wr (“Rd equals 1, Wr equals 0”), A/NA, 7-bit Addr; simple send “S Addr Wr [A] Data [A] … P”; receive ends “[Data] NA P”; combined transactions send “a start condition S” instead of a stop and continue
  2. Raspberry Pi Ltd, pico-sdk 1.5.1, hardware_i2c/i2c.h and i2c.c — “The first byte in the data transfer always contains the 7-bit address and a read/write bit in the LSB position”; nostop: “master retains control of the bus at the end of the transfer (no Stop is issued)”; returns “PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT”; up to fast mode plus, 1000 kb/s; i2c.c: i2c_reserved_addr(addr) is (addr & 0x78) == 0 or == 0x78; SCL low time 3/5 of the period
  3. Linux kernel, drivers/i2c/i2c-core-base.c and include/linux/i2c.h — i2c_parse_fw_timings: default maximum SCL rise time 1000 ns up to 100 kHz, 300 ns up to 400 kHz, 120 ns above, “derived from the I2C specification”; i2c_generic_scl_recovery gives “9 falling-rising edges” and creates a STOP; I2C_AQ_NO_CLK_STRETCH “clock stretching is not supported”
  4. Raspberry Pi Ltd, pico-examples, i2c/bus_scan/bus_scan.c — “I2C reserves some addresses for special purposes … any addresses of the form 000 0xxx or 111 1xxx”; enables gpio_pull_up on SDA and SCL; scans the 7-bit addresses, skipping the reserved ones, and marks those that acknowledge