Instructions, Registers, and the CPU

A processor core does one thing, forever:

1. Fetch the instruction stored at the address held in the program counter (PC).
2. Decode it: work out which operation it is and which registers or constants it names.
3. Execute it: do the arithmetic, the memory access or the comparison.
4. Advance the PC to the next instruction, unless the instruction was a branch, in which case the branch writes a new address into the PC.

That is the whole machine. Loops, function calls, interrupts and operating systems are all patterns of values written into the PC. The instructions themselves are just numbers in memory: on Arm Cortex-M cores most are 16-bit Thumb encodings, so the PC usually advances by 2; some are 32 bits wide and advance it by 4. The set of instructions a core understands, with their encodings and exact effects, is its instruction set architecture (ISA), and the architecture reference manual is its contract.

Memory is far away, on the other side of the bus. Inside the core is a small register file: a handful of words that can be read and written in the same cycle as an instruction executes. A 32-bit Arm core has sixteen of them, and the Arm procedure call standard (AAPCS32 §6.1.1) gives each a role so that separately compiled functions can call each other:

Alongside them sits a status register, the xPSR, whose top four bits are the condition flags N, Z, C and V (bits 31 to 28 in the CMSIS header for the Cortex-M0+).

Other architectures make different choices. RISC-V’s base integer ISA has 32 registers, x0 to x31, with x0 hardwired to zero so that “discard this result” and “use the constant 0” need no special instructions, and it keeps the PC outside the numbered registers. The idea is the same.

Arm Cortex-M and RISC-V are load–store architectures: arithmetic works only on registers, and the only instructions that access memory are loads (memory to register) and stores (register to memory). The RISC-V manual says it in one sentence; Arm’s Thumb instruction set is built the same way. So count = count + 1 on a global variable is three instructions, not one: load count into a register, add 1, store it back. Unit 2 lesson 6 showed what an interrupt between those three can do.

↑ This step uses the figure at the top of the page.

Step through the figure. The first two instructions load a and b from memory into r0 and r1, using r3, which already holds their address, as a base. ADDS adds registers and sets the flags. CMP subtracts 10 from r2 but throws the result away, keeping only the flags. BLE reads those flags and either jumps over the MOVS or does not. Finally STR writes r2 to c. Only instructions 1, 2 and 7 used the bus to reach data.

After a flag-setting instruction:

• N (negative) is a copy of bit 31 of the result.
• Z (zero) is 1 if the result is zero.
• C (carry) is 1 if an unsigned addition carried out of bit 31, or if an unsigned subtraction did not need to borrow (so after CMP x, y, C = 1 means $x \ge y$ as unsigned numbers).
• V (overflow) is 1 if the result is wrong as a signed two’s-complement number.

Conditional branches test combinations of these bits, and here unit 2’s signed/unsigned distinction becomes visible in the machine code. The comparison instruction is the same for both; only the branch differs:

Try $a = -5$, $b = 7$ in the figure. ADDS gives 2 with C = 1: as unsigned numbers, 0xFFFFFFFB + 7 carried out of bit 31. That carry is irrelevant for signed values, where V = 0 says the result is exact. The compiler emitted BLE because c is an int; had it been unsigned, the branch would have been BLS, testing C and Z instead. Declaring the wrong type changes which bits the processor looks at.

Assume a core with these cycle counts, typical of small Cortex-M cores running from zero-wait-state memory: loads and stores 2 cycles, register operations 1, a conditional branch 2 if taken and 1 if not. (Your core’s technical reference manual has the real table, and slower memory adds wait states: lesson 6.)

If $a + b \le 10$ the branch is taken and MOVS is skipped: LDR 2 + LDR 2 + ADDS 1 + CMP 1 + BLE 2 + STR 2 = 10 cycles for 6 instructions, CPI ≈ 1.67.

If $a + b > 10$ the branch falls through: 2 + 2 + 1 + 1 + 1 + MOVS 1 + 2 = 10 cycles for 7 instructions, CPI ≈ 1.43.

At 125 MHz one cycle is 8 ns, so either path takes $10 \times 8 = 80$ ns. The paths execute different numbers of instructions yet take the same time, which is why “count the lines” is not a timing method. And a single wait state on each of the three data accesses would add 3 cycles, 30 % more, without changing the instruction count at all.