Sleep States and Wake-Up Sources

A CMOS chip draws current in two ways. Every time a node switches, charge moves in and out of its capacitance: the dynamic power

$$P_{\text{dyn}} \approx \alpha\, C\, V^{2} f$$

grows with the clock frequency $f$, the switched capacitance $C$, the fraction $\alpha$ of it that switches each cycle, and the square of the supply voltage $V$. On top of that, transistors that are nominally off still leak: static power, present whenever the supply is on. An idle loop keeps every clock running, so it pays the full dynamic cost for nothing.

Three levers follow from the formula. Stop the clocks that are not needed (dynamic power falls to almost nothing for that block). Lower the voltage where the chip allows it; the pico-sdk’s vreg_set_voltage(), for example, sets the RP2040’s core regulator anywhere from 0.85 V to 1.30 V (1.10 V by default), and the $V^2$ term rewards every step down, though a lower voltage may not support the full clock speed. Switch power off to whole domains, which removes leakage too, at the cost of losing their state. Sleep states are packaged combinations of these levers.

On a Cortex-M the usual way in is one instruction: WFI (or WFE, unit 9). What the chip does when the core executes it depends on one bit, SLEEPDEEP in the System Control Register (SCB->SCR, bit 2), and on the vendor’s power controller, which decides what “deep” means on that chip. (The RP2040’s dormant state, below, is the exception: a register write enters it.)

↑ This step uses the figure at the top of the page.

The STM32F4 HAL’s power driver lists three states. Sleep (SLEEPDEEP clear) stops the core; peripherals keep running and any interrupt wakes it. Stop (SLEEPDEEP set) stops every clock in the 1.2 V core domain and the PLL and both high-speed oscillators, but keeps SRAM and registers; the regulator stays on, optionally in a low-power mode. Standby turns the core regulator off entirely, so SRAM and registers are lost apart from the RTC, its backup registers and the backup SRAM.

The RP2040 does it differently. It gates clocks through two registers, SLEEP_EN0 and SLEEP_EN1, that say which clocks stay on while the processor is in deep sleep; they reset to all ones, so a deep sleep with them untouched keeps every clock running. The sleep code in the pico-extras library first moves the system onto the crystal or ring oscillator and stops both PLLs, then clears the enables for everything except the RTC’s clock, sets SLEEPDEEP and executes WFI. Its dormant state goes further: writing a magic value to the oscillator’s DORMANT register stops the oscillator itself, and with it every clock derived from it.

The deeper the state, the less of the chip is awake to notice an event, so the list of wake-up sources shrinks:

Choose the state from the event, not the other way round. A UART in Stop mode has no clock, so it cannot receive the byte that should wake the system; the pin can be an EXTI line instead, but that first byte is lost unless the protocol repeats it. And look at what must happen after waking: an STM32 leaving Stop runs from its internal RC oscillator until firmware restarts the crystal and PLL, so a UART or timer configured for the PLL clock runs at the wrong rate until then. Standby is not a pause at all: the chip restarts, and the start-up code must look at the standby flag (PWR_FLAG_SB) to know it is waking rather than powering up.

Pins need thought too. In Sleep and Stop the STM32F4 keeps every pin in its state; in Standby most pins are high-impedance, so an output that held a MOSFET off now floats, and only an external pull resistor (unit 1, lesson 3) keeps it defined.

The obvious idle loop has a race:

while (!data_ready) {   /* the interrupt sets data_ready */
    __WFI();            /* if the interrupt fires between the test and here, */
}                       /* the core sleeps until the NEXT interrupt          */

If the interrupt arrives after the test but before WFI, its handler runs, sets the flag, and returns; the core then sleeps with the flag already set and nothing left to wake it. The fix relies on a property of WFI from unit 9: it wakes on a pending interrupt even when PRIMASK masks it. Mask interrupts, test, sleep, then unmask, so the handler runs after the wake-up instead of in the gap:

__disable_irq();        /* PRIMASK = 1: interrupts pend but do not run */
if (!data_ready)
    __WFI();            /* still wakes when the interrupt becomes pending */
__enable_irq();         /* the handler runs here */

FreeRTOS’s tickless idle for the Cortex-M0 does exactly this. When every task is blocked for at least a couple of ticks, vPortSuppressTicksAndSleep() executes cpsid i (the comment explains that its usual critical-section macro would mask the interrupts that must end the sleep), checks that no task has become ready, reprograms SysTick to fire at the end of the expected idle time instead of every tick, and only then executes wfi. Without tickless idle a 1 kHz tick would wake the chip a thousand times a second for nothing.

For designs that do everything in interrupt handlers, SLEEPONEXIT (SCR bit 1) sends the core back to sleep automatically on return from the last handler, without returning to the main loop at all.

A device must handle an event every 10 ms. Assume (illustratively) a light sleep at $I_l = 2$ mA that wakes instantly, and a deep sleep at $I_d = 20$ µA that takes $t_w = 2$ ms at $I_w = 5$ mA to wake.

The break-even gap is

$$T^{*} = 2\ \text{ms} \times \frac{5 - 0.02}{2 - 0.02} = 2\ \text{ms} \times 2.515 \approx 5.03\ \text{ms}$$

so the 10 ms gap is long enough. Averaged over one gap, deep sleep draws $0.02 + 4.98 \times 2/10 = 1.016$ mA against 2 mA: about half. With a 1 s gap the wake-up is spread thinner and deep sleep averages $0.02 + 4.98 \times 0.002 \approx 0.030$ mA, some 67 times less than light sleep. With a 3 ms gap it would average 3.34 mA, worse than not bothering. And if each event had to be answered within 1 ms, the 2 ms wake-up rules deep sleep out whatever the charge.